1. Field of the Invention
This invention relates to an improved single-shot circuit that functions both as a clock chopper and pulse shaper to generate a local clock signal from a master clock signal, and more particularly to a single-shot circuit with a fast reset.
2. Description of the Prior Art
In digital logic systems, single-shot circuits can function as a so-called clock chopper to generate on a chip local clock signals from a master clock signal. The master clock signals are generated by a common clock generator and these master clock pulses are distributed throughout the logic system to provide timing signals at a particular time within the repetitive clock cycle established by the master clock. The master clock pulses, however, may not be suitable for the purpose of controlling the operation of the circuits on a given chip in the digital logic system. In this case, a clock chopper circuit on the chip generates a suitable set of on-chip clock pulses from the system master clock input.
The single-shot circuit clock chopper creates an active output pulse of a predetermined width when triggered by an input signal edge. In response to a periodic input signal, the single shot should generate a series of active output pulses each with the same predetermined pulse width. The inactive period required by the single shot to correctly reset without changing the output pulse width determines the minimum period of the input pulses.
Such on-chip clocking circuits for certain logic designs must operate in two modes. The first required mode is a chop mode. The second requirement is that the on-chip clock pulse width must be measured in terms of frequency. The frequency measurement is accomplished by configuring the chopper circuit into a recirculating loop and measuring its characteristic frequency. This Recirculating Loop Frequency (RLF) mode of the chopper is required to improve the accuracy of the pulse width measurement. It is important that the RLF pulse measured is equal to the pulse generated during normal operation. When the time allowed for the delay element to recovery is different during RLF mode and normal mode, error will occur in the measurement of large pulse widths.
Clock Chopper circuits in current logic designs also must function as pulse shapers. The externally generated input clock pulse width is generally designed to be 50% of the cycle time. Since logic function times can often be more than 50% of cycle times, many logic designs require "stretched" pulses. The maximum pulse width that any pulse shaper can create is limited by the minimum time needed to reset the pulse shaper before a new pulse can be generated. The reset delay must be less than the pulse shaping delay in order to make a pulse greater than 50% of the cycle time.
Another concern arises when stretched pulses are being generated. The delay element used to form the pulse must have enough time to recover from making the last pulse before making the next pulse. A lack of sufficient recovery time often causes the first few pulses generated to be of different widths until a stable state is reached. The widest pulse that any pulse shaper can produce is determined by the reset time of the pulse shaper circuit and the recovery time of its delay element. The reset and recovery time becomes a crucial limitation to pulse shaper designs when cycle times become faster.
Several methods have been proposed in the prior art to address the reset and recovery time concern in clock chopper circuits. These include:
a. Two pulse shapers running at a slower cycle time and OR-ing result.
b. Forced reset of a chain of elements after pulse shaping.
c. OR-ing a chain of blocks together (One block high resets chopper).
The maximum width that can be created by these prior art methods is limited by the minimum reset time of the pulse shaper and the recovery time of the delay element. Methods b and c force the reset to be dominated by the recovery time of one delay block in a chain of delay blocks. Method 1, which can be used with a chain of delay blocks or one large delay element, doubles the recovery time allowed by dividing the cycle time in half. Method 1 also takes twice as much space as would Methods b or c and it requires an input clock divide by two circuit.
In a delay circuit that uses capacitive elements of a certain time constant to create a delay after each input signal swing, the delay through the circuit is constant only if the active elements are allowed to fully discharge or charge before switching again. If the circuit input signal is forcing the circuit to switch at a speed that is faster than the time constant of the storage device, then the circuit delay will vary with the switching speed of the input signal. In other words, the value of delay through the chain depends on the input stimulus duty cycle.
The recovery time concern becomes even more important when trying to use the clock circuits in RLF mode to measure array timings. The pulse width generated by the circuit can be varied until the appropriate timing is achieved. The circuit is then reconfigured to oscillate at a frequency that represents this pulse width, in order to do this, the delay chain is configured into a ring oscillator by inverting the output of the delay chain and feeding it back to the first block of the chain. The delay chain will then oscillate at the natural delay of the chain with a duty cycle of approximately 50%.